• DocumentCode
    814653
  • Title

    Single-clock, single-latch, scan design

  • Author

    Sheth, Amit M. ; Savir, Jacob

  • Author_Institution
    Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
  • Volume
    52
  • Issue
    5
  • fYear
    2003
  • Firstpage
    1455
  • Lastpage
    1457
  • Abstract
    This correspondence describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.
  • Keywords
    clocks; design for testability; flip-flops; logic design; logic testing; design for testability; single-clock single-latch scan design; test mode signal; Circuit testing; Clocks; Design for testability; Jacobian matrices; Latches; Logic; Master-slave; Pins; Proposals; Shift registers;
  • fLanguage
    English
  • Journal_Title
    Instrumentation and Measurement, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9456
  • Type

    jour

  • DOI
    10.1109/TIM.2003.818550
  • Filename
    1240157
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=814653