Polynomial evaluation in VLSI using distributed arithmetic

Alternate formulations of Horner´s rule which partitions the algorithm into inner-product computations are studied. Fixed-point inner products may be implemented with distributed arithmetic structures that use table-lookup in place of multiplication. Distributed arithmetic can be smaller and faster than lumped arithmetic in technologies where memory is cheaper than logic. The partitioned algorithms may be mapped to mesh-connected or tree-connected VLSI architectures. The partitions may be chosen to optimize cost measures and constraints that are functions of area, latency, period, and arithmetic precision. These structures are compared with a tree structure for polynomial evaluation. It is considered that each has advantages depending on problem size and target technology