• DocumentCode
    815513
  • Title

    On Concurrent Detection of Errors in Polynomial Basis Multiplication

  • Author

    Bayat-Sarmadi, Siavash ; Hasan, M. Anwar

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont.
  • Volume
    15
  • Issue
    4
  • fYear
    2007
  • fDate
    4/1/2007 12:00:00 AM
  • Firstpage
    413
  • Lastpage
    426
  • Abstract
    The detection of errors in arithmetic operations is an important issue. This paper discusses the detection of multiple-bit errors due to faults in bit-serial and bit-parallel polynomial basis (PB) multipliers over binary extension fields. Our approach is based on multiple parity bits. Experimental results presented here show that due to an increase in the number of parity bits, the area overhead tends to increase linearly, but the probability of error detection approaches unity fairly quickly, e.g., for eight parity bits. In bit-serial implementation of a GF(2163) PB multiplier using eight parity bits, the area overhead and the probability of error detection are 10.29% and 0.996, respectively. This is achieved without any increase in the computation time of the GF(2163) PB multiplier
  • Keywords
    digital arithmetic; error detection; logic testing; multiplying circuits; polynomials; area overhead; arithmetic operations; concurrent error detection; multiple-bit errors; parity bits; polynomial basis multiplication; Arithmetic; Circuit faults; Circuit testing; Elliptic curve cryptography; Fault detection; Galois fields; Hardware; Polynomials; System testing; Very large scale integration; Concurrent error detection (CED); finite fields; polynomial basis (PB) multiplication;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2007.893659
  • Filename
    4162502