Title :
VLSI Design of a Wavelet Processing Core
Author :
Lee, Sze-Wei ; Lim, Soon-Chieh
Author_Institution :
Fac. of Eng., Multimedia Univ., Selangor
Abstract :
A processing core architecture for the implementation of the discrete wavelet transform (DWT), optimized for throughput, scalability and programmability is proposed. The architecture is based on the RISC architecture with an instruction set specifically designed to facilitate the implementation of wavelet-based applications and a memory controller optimized for the memory access pattern of DWT processing
Keywords :
VLSI; discrete wavelet transforms; instruction sets; integrated circuit design; reduced instruction set computing; DWT; RISC architecture; VLSI design; discrete wavelet transform; instruction set; wavelet processing core; wavelet-based applications; Discrete wavelet transform (DWT); RISC architecture; VLSI design; parallel computing;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
DOI :
10.1109/TCSVT.2006.883507
