Title :
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS
Author :
Hoskote, Yatin ; Bloechel, Bradley A. ; Dermer, Gregory E. ; Erraguntla, Vasantha ; Finan, David ; Howard, Jason ; Klowden, Dan ; Narendra, Siva G. ; Ruhl, Greg ; Tschanz, James W. ; Vangal, Sriram ; Veeramachaneni, Venkat ; Wilson, Howard ; Xu, Jianping
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm2 experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.
Keywords :
CMOS digital integrated circuits; instruction sets; local area networks; microprocessor chips; special purpose computers; transport protocols; 1.72 V; 10 Gbit/s; 6.39 W; 64 byte; 90 nm; CMOS; Ethernet; TCP offload accelerator; hardware support; high-speed core; minimum packet size; out-of-order packets; packet processing performance; programmable engine; specialized instruction set; wire speed; Central Processing Unit; Ethernet networks; Hardware; Microprocessors; Open systems; Protocols; Prototypes; Search engines; TCPIP; Wire;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.818294
