Title :
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors
Author :
Osada, Kenichi ; Saitoh, Yoshikazu ; Ibe, Eishi ; Ishibashi, Koichiro
Author_Institution :
Syst. LSI Res. Dept., Hitachi Ltd., Tokyo, Japan
Abstract :
Tunnel-leakage currents become the dominant form of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multierrors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultralow-power 16-Mb SRAM. A test chip fabricated by using 0.13-μm CMOS technology showed per-cell standby-current values of 16.7 fA at 25°C and 101.7 fA at 90°C. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.
Keywords :
CMOS memory circuits; SRAM chips; cosmic ray interactions; error correction; integrated circuit testing; leakage currents; life testing; low-power electronics; neutron effects; 0.13 micron; 101.7 fA; 16 Mbit; 16.7 fA; 16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM; 25 C; 90 C; CMOS technology; MOS technology; accelerated neutron-exposure testing; cosmic-ray-induced multierrors; electric-field-relaxation scheme; error checking correction architecture; error handling; low standby current; per-cell standby-current; soft error reduction; test chip; tunnel-leakage currents; ultralow-power 16-Mb SRAM; CMOS technology; Circuits; Error correction; Error correction codes; Identity-based encryption; Laboratories; Leakage current; Random access memory; Sea level; Testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2003.818138
