Body tie placement in CMOS/SOI digital circuits for transient radiation environments

Author

Alles, M.L. ; Kerns, S.E. ; Massengill, Lloyd W. ; Clark, J.E. ; Jones, K.L., Jr. ; Lowther, R.E.

Author_Institution

Vanderbilt Univ., Nashville, TN, USA

Volume

38

Issue

6

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1259

Lastpage

1264

Abstract

The authors present criteria for the use of body ties to reduce or eliminate parasitic bipolar effects important in the transient radiation response of SOI/CMOS devices. A theoretically derived body tie spacing rule is verified using both TRIGSPICE and PISCES II with photocurrent injection capabilities. The tie spacing rule, which is independent of feature size within bounds, provides a simple guideline for design/layout for CMOS/SOI digital circuits for harsh transient radiation environment

Keywords

CMOS integrated circuits; digital integrated circuits; integrated circuit technology; radiation hardening (electronics); semiconductor-insulator boundaries; CMOS/SOI digital circuits; PISCES II; SOI/CMOS devices; TRIGSPICE; body tie placement; body tie spacing rule; harsh transient radiation environment; parasitic bipolar effects elimination; photocurrent injection capabilities; transient radiation environments; transient radiation response; Body regions; CMOS digital integrated circuits; Dielectric devices; Dielectric substrates; Digital circuits; Guidelines; Immune system; Photoconductivity; Resistors; Silicon on insulator technology;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.124102

Filename

124102