Modeling of radiation-induced leakage currents in CMOS/SOI devices

Author

Rios, R. ; Smeltzer, R.K. ; Garcia, G.A.

Author_Institution

David Sarnoff Res. Center, Princeton, NJ, USA

Volume

38

Issue

6

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1276

Lastpage

1281

Abstract

A new approach to model the effect of radiation-induced interface charges on silicon-on-insulator (SOI) devices has been implemented in a three-dimensional device simulation code. The model is validated by comparison of simulated and measured postradiation device characteristics. The applicability of the model is illustrated by analysis of standard and fully-depleted silicon-on-sapphire (SOS) devices. The results demonstrate and clarify the role of various bias conditions on parasitics in SOI structures and offer an explanation of the observed absence of back-channel conduction in fully-depleted nMOS-SOS transistors

Keywords

CMOS integrated circuits; digital simulation; radiation hardening (electronics); semiconductor device models; semiconductor-insulator boundaries; 3D device simulation code; CMOS/SOI devices; SOI structures; back channel conduction absence; bias conditions effect on parasitics; fully-depleted nMOS-SOS transistors; modeling; radiation-induced interface charges; radiation-induced leakage currents; Circuits; Equations; Isolation technology; Leakage current; Oceans; Photoconductivity; Sea measurements; Semiconductor device modeling; Silicon on insulator technology; Smelting;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.124105

Filename

124105