Optimization of the Porous-Silicon-Based Superjunction Power MOSFET

This paper discusses the optimization of a high-voltage superjunction (SJ) power MOSFET by the use of fabrication based on porous-silicon formation. In this fabrication process, the charge-compensating structures are created by etching the structured macropores directly on a thin silicon wafer, followed by passivating the walls and filling the pores with oppositely charged polysilicon. The effects of charge imbalance and the thickness of the passivation layer are studied by physically based numerical-device simulations. It is found that, even with small amount of charge imbalance, the proposed method can still produce high-voltage MOSFETs with much better performance than existing technology. A thick oxide layer between the p and n columns is found to be helpful in alleviating the junction field-effect transistor effects when the doping concentrations in the p and n columns are low. In comparison with a conventional SJ structure, the inclusion of an oxide layer between the p and n columns is found to help increase the device efficiency in addition to its ability to prevent dopant interdiffusion.