Title :
Bench-level characterization of a CMOS standard-cell D-latch using alpha-particle sensitive test circuits
Author :
Blaes, B.R. ; Soli, G.A. ; Buehler, M.G.
Author_Institution :
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA
fDate :
12/1/1991 12:00:00 AM
Abstract :
A methodology is described for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. Measurements were made on a 1.6-μm n-well CMOS 4-kb test SRAM irradiated with an Am-241 alpha-particle source. A collection depth of 6.09 μm was determined using these results and TRIM computer code. Using this collection depth and SPICE derived critical charge results on the latch design, an LET threshold of 34 MeV cm2/mg was predicted. Heavy ion tests were then performed on the latch and an LET threshold of 41 MeV cm2/mg was determined
Keywords :
CMOS integrated circuits; SRAM chips; alpha-particle effects; integrated circuit testing; 1.6 micron; 4 kbit; CMOS standard-cell D-latch; LET threshold; SEU susceptibility; SPICE critical charge simulation; TRIM computer code; alpha-particle interaction physics; alpha-particle sensitive test circuits; bench level characterization; collection depth; heavy ion tests; n-well CMOS SRAM; Alpha particles; Circuit testing; Laboratories; Latches; MOSFET circuits; Propulsion; Random access memory; SPICE; System testing; Threshold voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on