Analysis and design of a new race-free four-phase CMOS logic

A four-phase dynamic logic, called the high-speed precharge-discharge CMOS (HS-PDCMOS) logic, is proposed and analyzed. Basically, the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus, a complex function can be implemented within a single gate and form the pipelined structure as well. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to partly verify the results of circuit analysis and simulation. It is shown that the HS-PDCMOS logic has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the logic has no clock skew, race, and charge redistribution problems. These advantages make the HS-PDCMOS logic very promising in high-speed complex VLSI design