Post irradiation effects (PIE) in integrated circuits [CMOS]

Author

Shaw, D.C. ; Lowry, L. ; Barnes, C. ; Zakharia, M. ; Agarwal, S. ; Rax, B.

Author_Institution

Jet Propulsion Lab.. California Inst. of Technol., Pasadena, PA, USA

Volume

38

Issue

6

fYear

1991

fDate

12/1/1991 12:00:00 AM

Firstpage

1584

Lastpage

1589

Abstract

Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI 1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI 1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si)

Keywords

CMOS integrated circuits; environmental testing; failure analysis; gamma-ray effects; integrated circuit testing; stress measurement; stress relaxation; CMOS technology; HI 1-507A analog multiplexer; MIL-STD Method 1019.4; PIE period; X-ray diffraction; catastrophic failure; integrated circuits; metallization; physical stress measurement; post irradiation effects; radiation effects; rebound; recovery; stress relaxation; Annealing; CMOS integrated circuits; CMOS technology; Interface states; Laboratories; Space missions; Space technology; Temperature; Testing; Threshold voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/23.124149

Filename

124149