Response of interface traps during high-temperature anneals [MOSFETs]

Isochronal-annealing measurements were performed on n-channel Si-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) to determine the temperature at which interface traps anneal following exposure to 10-keV X-rays. All five of the processes sampled exhibited annealing by 300°C, although this annealing was generally preceded by an increase in the number of interface traps (N_IT) at lower temperatures. In particular, N _IT for two of the processes increased at 100°C. Additional annealing experiments at 100°C for a week are consistent with these results. The implications of these results for high-temperature accelerated-annealing rebound testing are discussed