Analysing trade-offs in scan power and test data compression for systems-on-a-chip

The relationship is investigated between test data compression and power dissipation during scan testing. It is shown how combining a proposed symmetric coding scheme and a weighted scan latch reordering (W-SLR) algorithm allows efficient exploration of the scan power and test data compression solution space. This is achieved by reducing and balancing the transition activity in the scan-in and scan-out sequences. This will impact the test data compression, which depends only on the scan-in sequence, and the overall scan power dissipation, which depends on the scan-in and scan-out sequences. Trade-off analysis using ISCAS89 benchmark circuits shows that, by employing the proposed symmetric coding scheme and varying a weighting parameter in the W-SLR algorithm, the embedded core designer can easily and explicitly control the scan power and volume of test data. The proposed asymmetric/symmetric code transformation is equally applicable to (and thus it maintains its benefits) any asymmetric ´run length´ coding scheme