Simulation of a new back junction approach for reducing charge collection in 200 GHz SiGe HBTs

We present a new back junction approach for reducing SEU-induced charge collection in SiGe HBTS, and demonstrate its effectiveness in a state-of-the-art 200 GHz SiGe HBT using full 3-D device simulation. An additional n⁺ layer is used below the p-type isolation layer to form a back junction. The back junction limits potential funneling to within the p-type layer, which effectively limits the total amount of drift charge collection that is now shared by the collector-to-substrate junction and the back junction. The back junction also cuts off the diffusion charge coming from the substrate, further limiting charge collection by the HBT collector. A thinner p-type "substrate" layer and a better contact to the added n⁺ layer are shown to help reduce charge collection by the HBT collector, the sensitive node.