Binary Integer Decimal-Based Floating-Point Multiplication

Author

Gonzalez-Navarro, S. ; Tsen, C. ; Schulte, M.J.

Author_Institution

Dept. of Comput. Archit., Univ. of Malaga, Malaga, Spain

Volume

62

Issue

7

fYear

2013

fDate

Jul-13

Firstpage

1460

Lastpage

1466

Abstract

This paper presents a multiplier that operates on binary integer decimal (BID) encoded decimal floating-point (DFP) numbers. It uses a single binary multiplier with carry-save feedback for both significand multiplication and rounding, and it is compliant with the IEEE 754-2008 Standard. Optimizations decrease the BID multiplier´s area and critical path delay.

Keywords

carry logic; floating point arithmetic; logic design; multiplying circuits; BID encoded DFP numbers; BID multiplier area; IEEE 754-2008 standard; binary integer decimal-based floating-point multiplication; carry-save feedback; critical path delay; decimal floating-point numbers; rounding; significand multiplication; single binary multiplier; Decision support systems; Decoding; Delay; Hardware; Indexes; Optimization; Table lookup; BID encoded DFP numbers; BID multiplier area; Binary integer decimal; Decision support systems; Decoding; Delay; Hardware; IEEE 754-2008; IEEE 754-2008 standard; Indexes; Optimization; Table lookup; binary integer decimal-based floating-point multiplication; carry logic; carry-save feedback; carry-save multiplier; computer arithmetic; critical path delay; decimal floating-point; decimal floating-point numbers; floating point arithmetic; hardware designs; logic design; multiplication; multiplying circuits; rounding; significand multiplication; single binary multiplier;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.2012.79

Filename

6178239