Title :
Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM
Author :
Bard, K. ; Dewey, B. ; Mei-Ting Hsu ; Mitchell, T. ; Moody, K. ; Rao, V. ; Rose, R. ; Soreff, J. ; Washburn, S.
Author_Institution :
IBM Electron. Design Autom., Fishkill, NY
fDate :
3/1/2007 12:00:00 AM
Abstract :
IBM´s high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a transistor width tuner that optimizes performance and area. We also describe the application of electrical rule checking used to enforce consistent design practices. Finally, we discuss a macro extraction tool that determines parasitic resistance and capacitance of interconnect from a layout
Keywords :
electronic design automation; microprocessor chips; IBM; consistent design practices; custom circuit design; electrical rule checking; electronic design automation tools; embedded simulation; high-end processor; high-frequency microprocessor; high-performance microprocessor; macro extraction tool; power efficient microprocessor; robust microprocessors; sensitivity computation; static noise analysis; transistor width tuning; transistor-level block-based static timing; transistor-level tools; Circuit noise; Circuit synthesis; Electric resistance; Electronic design automation and methodology; Microprocessors; Noise robustness; Optimization methods; Parasitic capacitance; Performance analysis; Tuners; Electrical rule checking; LVS; embedded simulation; macro extraction; sensitivity computation; static noise analysis; static transistor-level timing; transistor width tuning;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/JPROC.2006.889385