Title :
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode
Author :
Wei Zhang ; Ki Chul Chun ; Kim, Chul Han
Author_Institution :
Dept. of ECE, Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
A gain cell embedded DRAM (eDRAM) in a 65 nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local voltage sense amplifiers. A low-overhead dual-row access mode improves the worst-case cell retention time by 3X, minimizing standby power at times when only a fraction of the entire memory is utilized. Measurement results from a 64 kb eDRAM test chip in 65 nm CMOS demonstrate the effectiveness of the proposed circuit techniques.
Keywords :
CMOS integrated circuits; DRAM chips; low-power electronics; CMOS; LP process; dual-row-access low power mode; frequency 1.0 GHz; local voltage sensing; low-overhead dual-row access mode; random read access frequency; read bitline swing; size 65 nm; worst-case cell retention time; write-back operation; write-back-free 2T1D embedded DRAM; Dual row access; embedded DRAM; gain cell; local sense amplifier; low power; write-back-free read;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2013.2252652