HBD layout isolation techniques for multiple node charge collection mitigation

Author

Black, Jeffrey D. ; Sternberg, Andrew L. ; Alles, Michael L. ; Witulski, Arthur F. ; Bhuva, Bharat L. ; Massengill, Lloyd W. ; Benedetto, Joseph M. ; Baze, Mark P. ; Wert, Jerry L. ; Hubert, Matthew G.

Author_Institution

Inst. of Space & Defense Electron., Vanderbilt Univ., Nashville, TN, USA

Volume

52

Issue

6

fYear

2005

Firstpage

2536

Lastpage

2541

Abstract

A three-dimensional (3D) technology computer-aided design (TCAD) model was used to simulate charge collection at multiple nodes. Guard contacts are shown to mitigate the charge collection and to more quickly restore the well potential, especially in PMOS devices. Mitigation of the shared charge collection in NMOS devices is accomplished through isolation of the P-wells using a triple-well option. These techniques have been partially validated through heavy-ion testing of three versions of flip-flop shift register chains.

Keywords

MOS integrated circuits; flip-flops; isolation technology; radiation hardening (electronics); shift registers; technology CAD (electronics); 3D technology; NMOS devices; PMOS devices; charge collection mitigation; computer-aided design model; flip-flop shift registers; guard contacts; hardness-by-design layout isolation techniques; heavy-ion testing; multiple node; single-event effects; Computational modeling; Computer simulation; Design automation; Imaging phantoms; Isolation technology; Latches; MOS devices; Potential well; Single event upset; Testing; Guard contacts; single-event effects; technology computer-aided design (TCAD) modeling;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2005.860718

Filename

1589235