Title :
Embedded test control schemes using iBIST for SOCs
Author :
Kay, Douglas ; Chung, Sung ; Mourad, Samiha
Author_Institution :
Cisco Syst., San Jose, CA, USA
fDate :
6/1/2005 12:00:00 AM
Abstract :
This paper presents novel control schemes for testing embedded cores in a system-on-a-chip. It converts a traditional built-in self-test (BIST) scheme into an externally controllable scheme to achieve high test quality within optimal test execution time without inserting test points. Interactive BIST promotes design and test reuse without revealing IP information by using a pattern matching technique instead of fault simulation.
Keywords :
built-in self test; embedded systems; integrated circuit testing; pattern matching; system-on-chip; SOC; built-in self-test; embedded core testing; embedded test control; iBIST; interactive BIST; pattern matching; system-on-a-chip; Automatic testing; Bandwidth; Built-in self-test; Circuit faults; Circuit testing; Costs; Fault detection; System testing; System-on-a-chip; Test pattern generators; Algorithms; built-in self-test (BIST); data compression; design; experimentation; performance; test resource allocation;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
DOI :
10.1109/TIM.2005.847349
