Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement

Timing measurements for gigahertz clock frequencies require high accuracy and resolution. This paper proposes a scalable built-in self-test (BIST) method that measures accumulated period jitter over a programmable number of periods, without using another reference clock. This on-chip method uses a charge pump to convert time to a voltage, which is digitized by an all-digital flash analog-to-digital converter (ADC). The ADC employs multiple chains of inverter strings composed of three series inverters instead of the popular analog comparators. The inverter thresholds set the reference voltages for triggering given an input dc value. The output is calibrated and converted to jitter measurement. The design using a 0.25 μm BiCMOS process, with an input range of 625 MHz-1 GHz, shows that a resolution of 70 ps root mean square (rms) jitter can be achieved, while occupying 0.0575 mm² area with a very conservative layout style. The design has been fabricated and tested, and the test results are presented.