A built-in-test scheme for evaluating the parameters of floating-gate MOS transistors

Author

Hou, An Sang

Author_Institution

Dept. of Electron. Eng., Southern Taiwan Univ. of Technol., Tainan Hsien, Taiwan

Volume

54

Issue

3

fYear

2005

fDate

6/1/2005 12:00:00 AM

Firstpage

988

Lastpage

995

Abstract

In this paper, analog multiplexers, biasing circuit, decoders, a 16-bit analog-to-digital (A/D) converter, and a 32-bit advanced reduced instruction set computer (RISC) machine are employed to achieve a built-in-test scheme for evaluating the parameters of several floating-gate MOS transistors (FGTs). The feedback technology is applied so the parameters of FGTs can be evaluated with good accuracy. The proposed scheme does not require any matched components, and thus, it can be applied effectively to evaluate the parameters of multiple FGTs. The sampling time for each FGT is estimated to be 4.8 ms. Examples of analog-circuit applications are addressed to emphasize the necessity of the proposed scheme. Dynamic responses and static characteristics are demonstrated with experimental results.

Keywords

MOSFET; analogue circuits; automatic test equipment; built-in self test; semiconductor device testing; 16 bit; 32 bit; advanced reduced instruction set computer; analog multiplexers; analog-to-digital converter; biasing circuit; built-in-test; decoders; floating-gate MOS transistors; parameter evaluation; Analog computers; Analog-digital conversion; Circuits; Computer aided instruction; Decoding; Feedback; MOSFETs; Multiplexing; Reduced instruction set computing; Sampling methods; Advance reduced instruction set computer (RISC) machine; built-in test; capacitance ratio; floating-gate MOS transistor; threshold voltage;

fLanguage

English

Journal_Title

Instrumentation and Measurement, IEEE Transactions on

Publisher

ieee

ISSN

0018-9456

Type

jour

DOI

10.1109/TIM.2005.847338

Filename

1433169