Title :
Built-in self-test for phase-locked loops
Author :
Hsu, Chun-Lung ; Lai, Yiting ; Wang, Shu-Wei
Author_Institution :
Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan
fDate :
6/1/2005 12:00:00 AM
Abstract :
An effective built-in self-test (BIST) structure of a phase-locked loop (PLL) in digital applications is presented in this paper. The proposed BIST structure can identify possible faults in any block such as the phase detector, charge pump, loop filter, voltage-controlled oscillator and divide-by-N of the PLL. The key advantage of this approach is that it uses all existing blocks in PLL for measuring and testing, reducing the chip area overhead. Restated, the proposed approach does not alter any existing analog circuits. Rather, the proposed approach only adds some small circuits to the PLL and requires a slight modification of the digital part. The final test outputs are digital values which can increase the reliability of the proposed BIST structure. Physical chip design and fault simulation results indicate the characteristics of the proposed BIST structure, namely, high fault coverage (97.2%) and low area overhead (2.78%).
Keywords :
built-in self test; digital phase locked loops; integrated circuit testing; BIST; PLL; built-in self-test; phase-locked loops; Built-in self-test; Charge pumps; Circuit faults; Circuit testing; Detectors; Electrical fault detection; Fault detection; Fault diagnosis; Phase detection; Phase locked loops; Area overhead; built-in self-test (BIST); fault coverage; phase-locked loop (PLL); testing;
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
DOI :
10.1109/TIM.2005.847343