• DocumentCode
    819724
  • Title

    Low power adiabatic programmable logic array with APDL-2

  • Author

    Yang, W.J. ; Zhou, Y. ; Lau, K.T.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore
  • Volume
    39
  • Issue
    21
  • fYear
    2003
  • Firstpage
    1501
  • Lastpage
    1502
  • Abstract
    A novel low power programmable logic array (PLA) structure based on adiabatic switching is presented. Simulation results show that the power consumption is similar to that of the adiabatic pseudo-domino logic (APDL) PLA, but while standard transistor sizing for the isolation transistor can be applied, in APDL PLA this transistor was designed with a larger width.
  • Keywords
    CMOS logic circuits; low-power electronics; programmable logic arrays; APDL-2; adiabatic pseudo-domino logic circuit structure; adiabatic switching; low power PLA structure; low power programmable logic array; power consumption; standard sized isolation transistor;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20030994
  • Filename
    1242794
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=819724