DocumentCode
819927
Title
High-sensitivity decision circuit in InP/InGaAs DHBT technology and 40-80 Gbit/s optical experiments
Author
Konczykowska, A. ; Jorge, F. ; Kasbari, A. ; Idler, W. ; Giraudet, L. ; Schuh, K. ; Junginger, B. ; Godin, J.
Volume
39
Issue
21
fYear
2003
Firstpage
1532
Lastpage
1533
Abstract
A high-input-sensitivity (30 mV) decision D flip-flop (DFF) IC fabricated in a self-aligned InP DHBT technology is presented. Full- and half-rate phase margin at 43 Gbit/s were measured. Two optical receiver experiments using this decision DFF for 40 Gbit/s NRZ (full-rate) and 80 Gbit/s RZ (half-rate) data are also presented.
Keywords
III-V semiconductors; bipolar digital integrated circuits; decision circuits; digital communication; error statistics; flip-flops; gallium arsenide; heterojunction bipolar transistors; high-speed integrated circuits; indium compounds; optical receivers; sensitivity; 30 mV; 40 Gbit/s; 80 Gbit/s; BER measurements; D flip-flop IC; InP-InGaAs; InP/InGaAs DHBT technology; bit error rate; high-sensitivity decision circuit; high-speed decision DFF; optical receiver experiments; self-aligned HBT technology;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20030941
Filename
1242814
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