Design of a Digital Logarithmic Ratemeter Circuit

The state of a binary counter that has accumulated pulses is digitally converted to a logarithmic representation to base 2. The characteristic is determined by a shift register which locates the leading bit. A 3-bit mantissa over a factor of 2 is generated by a logic look-up table from the second to the fifth most significant bits. The root mean square error in the mantissa is 2.7% and the maximum error is 6.6%. The output signal is derived from a digital-to-analog converter. In a particular application where the analog output is displayed on a 5-decade scale for counting rates from 0.1 s-1 to 104 s-1, the maximum error from conversion is less than 1% of full-scale reading. Up to 8 decades may be displayed. The minimum counts to be accumulated before conversion, and hence the statistical accuracy, may be preset. The shortest counting time is 5s but longer times, up to 640s, are automatically allowed in order to satisfy a preset count limit.