Title :
Design, selection and implementation of flash erase EEPROM memory cells
Author_Institution :
Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
fDate :
6/1/1992 12:00:00 AM
Abstract :
The author reports an investigation into the design and process constraints of flash EEPROM memory cells. He describes several possible structures which were developed by the MOS memory R&D group of National Semiconductor Corporation at West Jordan, Utah. These structures were implemented and tested on a specially designed test chip. In addition to the typical structures of poly 1 floating gate and poly 2 control gate, new novel structures of poly 2 floating gate and poly 1 control gate were implemented. A total of five major structures are described. The author discusses the principle of operation, advantages and disadvantages of each of these structures. Also included are characteristic results and a discussion of the performance of these candidate cells
Keywords :
CMOS integrated circuits; EPROM; integrated memory circuits; EEPROM memory cells; MOS memory; flash erase; n-well CMOS process; poly 1 control gate; poly 1 floating gate; poly 2 control gate; poly 2 floating gate; test chip;
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings G
