Title :
Clock duty cycle adjuster circuit for switched capacitor circuits
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fDate :
8/29/2002 12:00:00 AM
Abstract :
A pulse width locked loop, which can be used to generate an output clock with a wide range of duty cycle (25 to 75%) precisely, from a single-ended input clock with any duty cycle (25 to 75%) is explained. Measurement results of an application of this loop, in pipelined data converters, are reported
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; clocks; pipeline processing; pulse shaping circuits; switched capacitor networks; CMOS process; clock duty cycle adjuster circuit; output clock generation; pipelined analogue-to-digital converter; pipelined data converters; pulse width locked loop; single-ended input clock; switched capacitor circuits; wide duty cycle range;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020657
