DocumentCode
820773
Title
Reconfigurable hardware implementation of BinDCT
Author
Murphy, C.W. ; Harvey, D.M.
Author_Institution
Sch. of Eng., Liverpool John Moores Univ., UK
Volume
38
Issue
18
fYear
2002
fDate
8/29/2002 12:00:00 AM
Firstpage
1012
Lastpage
1013
Abstract
Enhancing the coding gain and operand throughput of a data compression application through dynamic hardware reconfiguration is described. A novel implementation of the BinDCT, a discrete cosine transform (DCT) approximation has been realised on a run-time reconfigurable custom XC6200 field programmable gate array-based dynamic coprocessor, coupled to a TMS320C40 digital signal processor system
Keywords
coprocessors; digital signal processing chips; discrete cosine transforms; field programmable gate arrays; image coding; reconfigurable architectures; BinDCT; TMS320C40 digital signal processor system; Xilinx XC6200 field programmable gate arrays; coding gain; data compression; discrete cosine transform approximation; dynamic hardware reconfiguration; operand throughput; reconfigurable hardware implementation; run-time reconfigurable custom XC6200 FPGA-based dynamic coprocessor;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20020711
Filename
1033241
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