Title :
VLSI architecture for block-matching motion estimation algorithm
Author :
Hsieh, Chaur-Heh ; Lin, Ting-Pang
Author_Institution :
Dept. of Electr. Eng., Chung Cheng Univ., Taoyuan, Taiwan
fDate :
6/1/1992 12:00:00 AM
Abstract :
The block-matching motion estimation is the most popular method for motion-compensated coding of image sequence. A VLSI architecture for implementing a full-search block-matching algorithm is presented. Based on a systolic array processor and shift register arrays with programmable length, the proposed architecture has the following advantages: it allows serial data input to save the pin counts but performs parallel processing; it is flexible in adaptation to the dimensional change of the search area via simple control; it can operate in real time for videoconference applications; and it is simple and modular in design, and thus is suitable for VLSI implementation
Keywords :
VLSI; computerised picture processing; encoding; systolic arrays; CMOS technology; VLSI architecture; block-matching motion estimation algorithm; image coding; image sequence; modular design; motion-compensated coding; parallel processing; programmable length; real time operation; serial data input; shift register arrays; systolic array processor; videoconference applications; Adaptive arrays; Hardware; Image coding; Motion estimation; Parallel processing; Shift registers; Very large scale integration; Video codecs; Video coding; Videoconference;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
