Design and hardware architecture of high-order conditional entropy coding for images

High-order conditional entropy coding has not been practical due to its high complexity and lack of hardware to extract the conditioning state efficiently. The authors adopt the recently developed incremental-tree-extension technique to design the conditional tree for high-order conditional entropy coding. In order to make the high-speed conditional entropy coder feasible, they introduce several key innovations in the areas of complexity reduction and hardware architecture. For complexity reduction, they develop two techniques: code table reduction and nonlinear quantization of conditioning pixels. For hardware architecture, they propose a pattern-matching technique for fast conditioning state extraction and a multistage pipelined structure to handle the case of a large number of conditioning pixels. Using the complexity reduction techniques and the hardware structures. the authors demonstrate that it is possible to implement practical high-order conditional entropy codecs using current low-cost very large-scale integration (VLSI) technology