Title :
Chrominance/luminance signal separation and syntheses chips developed with a DSP silicon compiler
Author :
Miyazaki, Takashi ; Nishitani, Takao ; Ishikawa, Masaki ; Edahiro, Masato ; Mitsuhashi, Kaoru
Author_Institution :
NEC Corp., Kawasaki, Japan
fDate :
6/1/1992 12:00:00 AM
Abstract :
VLSI chips for luminance/chrominance (Y/C) signal separation and synthesis have been developed. Application-specific FIR filter structures and canonical signed-digit representation (CSR) multipliers used in the filters make it possible to develop compact high-speed VLSI chips. A silicon compiler, which employs the optimal FIR filter structures and supplies the optimal filter design faculty, has contributed to quick VLSI development. Y/C signal separation using four video FIR filters and Y/C signal synthesis using three video FIR filters are implemented on single chips by 1.2-μm CMOS technology
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; digital filters; digital signal processing chips; signal synthesis; video signals; 1.2 micron; 1.2-μm CMOS technology; DSP silicon compiler; FIR filter structures; VLSI chips; luminance/chrominance signal separation; multipliers; optimal filter design; signal synthesis; video FIR filters; Digital signal processing; Digital signal processing chips; Finite impulse response filter; Signal processing; Signal synthesis; Silicon compiler; Source separation; TV; Very large scale integration; Videoconference;
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
