DocumentCode
821430
Title
The state of VLSI testing
Author
Patnaik, L.M. ; Jamadagni, H.S. ; Agrawal, V.K. ; Varaprasad, B.K.S.V.L.
Author_Institution
Dept. of Comput. Sci. & Autom., Indian Inst. of Sci., Bangalore, India
Volume
21
Issue
3
fYear
2002
Firstpage
12
Lastpage
16
Abstract
The phenomenal development in electronic systems has, in large part, the advances in Very Large Scale of Integration (VLSI) semiconductor technologies to thank. Performance, area, power and testing are some of the most important improvements. With the reduction in device sizes, it is becoming possible to fit increasingly larger number of transistors onto a single chip. However, as chip density increases, the probability of defects occurring in a chip increases as well. Thus, the quality, reliability and cost of the product are directly related to the intensity/level of testing of the product. As a result, gradually, Integrated Circuits (ICs) testing has shifted from the final fabricated ICs to the design stage. In this context, many Design For Testability (DFT) techniques have been developed to ease the testing process.
Keywords
VLSI; design for testability; integrated circuit testing; VLSI testing; design for testability; electronic system; integrated circuit; Circuit faults; Circuit noise; Circuit testing; Clocks; Crosstalk; Digital circuits; Logic; Power supplies; Propagation delay; Very large scale integration;
fLanguage
English
Journal_Title
Potentials, IEEE
Publisher
ieee
ISSN
0278-6648
Type
jour
DOI
10.1109/MP.2002.1033655
Filename
1033655
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