DocumentCode
821656
Title
Implementation of a new neurochip using stochastic logic
Author
Sato, Shigeo ; Nemoto, Ken ; Akimoto, Shunsuke ; Kinjo, Mitsunaga ; Nakajima, Koji
Author_Institution
Lab. for Electron. Intelligent Syst., Tohoku Univ., Sendai, Japan
Volume
14
Issue
5
fYear
2003
Firstpage
1122
Lastpage
1127
Abstract
Even though many neurochips have been developed and investigated, the best suitable way for implementation has not been known clearly. Our approach is to exploit stochastic logic for various operations required for neural functions. The advantage of stochastic logic is that complex operations can be implemented with a few ordinary logic gates. On the other hand, the operation speed is not so fast since stochastic logic requires certain accumulation time for averaging. However, a huge integration can be achieved and its reliability is high because all of operations are done on digital circuits. Furthermore, we propose a nonmonotonic neuron realized by stochastic logic, since the nonmonotonic property is efficient for the performance enhancement in association and learning. In this paper, we show the circuit design and measurement results of a neurochip comprising 50 neurons are shown. The advantages of nonmonotonic and stochastic properties are shown clearly.
Keywords
Boltzmann machines; formal logic; integrated logic circuits; large scale integration; neural chips; simulated annealing; travelling salesman problems; Boltzmann machine; LSI; large-scale integration; neural chips; nonmonotonic neuron; simulated annealing; stochastic logic; traveling salesman problem; Artificial neural networks; Circuit synthesis; Digital circuits; Integrated circuit measurements; Integrated circuit reliability; Large scale integration; Logic gates; Neural networks; Neurons; Stochastic processes;
fLanguage
English
Journal_Title
Neural Networks, IEEE Transactions on
Publisher
ieee
ISSN
1045-9227
Type
jour
DOI
10.1109/TNN.2003.816341
Filename
1243715
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