Title :
0.8 μm CMOS implementation of weighted-order statistic image filter based on cellular neural network architecture
Author_Institution :
Inst. of Electron., Tech. Univ. of Lodz, Poland
Abstract :
In this paper, a very large scale integration chip of an analog image weighted-order statistic (WOS) filter based on cellular neural network (CNN) architecture for real-time applications is described. The chip has been implemented in CMOS AMS 0.8 μm technology. CNN-based filter consists of feedforward nonlinear template B operating within the window of 3 × 3 pixels around the central pixel being filtered. The feedforward nonlinear CNN coefficients have been realized using programmable nonlinear coupler circuits. The WOS filter chip allows for processing of images with 300 pixels horizontal resolution. The resolution can be increased by cascading of the chips. Experimental results of basic circuit building blocks measurements are presented. Functional tests of the chip have been performed using a special test setup for PAL composite video signal processing. Using the setup real images have been filtered by WOS filter chip under test.
Keywords :
CMOS analogue integrated circuits; VLSI; application specific integrated circuits; cellular neural nets; feedforward neural nets; image processing; neural chips; neural net architecture; real-time systems; CMOS; CNN-based filter; WOS filter chip; application specific integrated circuit; cellular neural network architecture; composite video signal processing; experimental results; feedforward nonlinear neural network; feedforward nonlinear template; image processing; pixels; programmable nonlinear coupler circuits; real-time applications; very large scale integration chip; weighted-order statistic image filter; CMOS technology; Cellular neural networks; Circuit testing; Coupling circuits; Filters; Image resolution; Pixel; Signal resolution; Statistics; Very large scale integration;
Journal_Title :
Neural Networks, IEEE Transactions on
DOI :
10.1109/TNN.2003.816384