DocumentCode :
821885
Title :
Kerneltron: support vector "machine" in silicon
Author :
Genov, Roman ; Cauwenberghs, Gert
Author_Institution :
Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA
Volume :
14
Issue :
5
fYear :
2003
Firstpage :
1426
Lastpage :
1434
Abstract :
Detection of complex objects in streaming video poses two fundamental challenges: training from sparse data with proper generalization across variations in the object class and the environment; and the computational power required of the trained classifier running real-time. The Kerneltron supports the generalization performance of a support vector machine (SVM) and offers the bandwidth and efficiency of a massively parallel architecture. The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions. At the core of the Kerneltron is an internally analog, fine-grain computational array performing externally digital inner-products between an incoming vector and each of the stored support vectors. The three-transistor unit cell in the array combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Precise digital outputs are obtained through oversampled quantization of the analog array outputs combined with bit-serial unary encoding of the digital inputs. The 256 input, 128 vector Kerneltron measures 3 mm×3mm in 0.5 μm CMOS, delivers 6.5 GMACS throughput at 5.9 mW power, and attains 8-bit output resolution.
Keywords :
VLSI; generalisation (artificial intelligence); learning (artificial intelligence); learning automata; matrix multiplication; neural chips; object detection; parallel architectures; real-time systems; CMOS; GMACS; Kerneltron; VLSI; bandwidth; binary multiplication; bit-serial unary encoding; complex object detection; computational array; dynamic random-access memory; generalization; massively parallel architecture; matrix-vector multiplication; mixed-signal very large-scale integration; pattern recognition; real-time; single-bit dynamic storage; streaming video; support vector machine; throughput; vector quantization; zero-latency analog accumulation; Bandwidth; Kernel; Large scale integration; Object detection; Parallel architectures; Silicon; Streaming media; Support vector machine classification; Support vector machines; Very large scale integration;
fLanguage :
English
Journal_Title :
Neural Networks, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9227
Type :
jour
DOI :
10.1109/TNN.2003.816345
Filename :
1243738
Link To Document :
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