Abstract :
The Chinese remainder theorem (CRT) and mixed-radix conversion (MRC) are two classic theorems used to convert a residue number to its binary correspondence for a given moduli set {P n,...,P 2, P 1}. The MRC is a weighted number system and it requires operations modulo P i only and hence magnitude comparison is easily performed. However, the calculation of the mixed-radix coefficients in the MRC is a strictly sequential process and involves complex divisions. Thus the residue-to-binary (R/B) conversions and residue comparisons based on the MRC require large delay. In contrast, the R/B conversion and residue comparison based on the CRT are fully parallel processes. However, the CRT requires large operations modulo M = P n,...,P 2 P 1. In this paper, a new mixed-radix CRT is proposed which possesses both the advantages of the CRT and the MRC, which are parallel processing, small operations modulo P i only, and the efficiency of making modulo comparison. Based on the proposed CRT, new residue comparators are developed for the three-moduli set {2n - 1, 2n, 2n + 1}. The FPGA implementation results show that the proposed modulo comparators are about 20% faster and smaller than one of the previous best designs.
Keywords :
field programmable gate arrays; residue number systems; FPGA; binary correspondence; mixed-radix Chinese remainder theorem; mixed-radix conversion; parallel processing; residue comparison; residue-to-binary conversions; sequential process; Arithmetic; Bismuth; Cathode ray tubes; Concurrent computing; Delay; Digital signal processing; Field programmable gate arrays; Parallel processing; Read only memory; Table lookup; Chinese Remainder Theorem; Computer arithmetic; FPGA; Mixed-Radix conversion; RNS; Residue comparison.; Residue number system;
