• DocumentCode
    822162
  • Title

    Parallel micro genetic algorithm for constrained economic dispatch

  • Author

    Tippayachai, Jarurote ; Ongsakul, Weerakorn ; Ngamroo, Issarachai

  • Author_Institution
    Sirindhorn Int. Inst. of Technol., Thammasat Univ., Thailand
  • Volume
    17
  • Issue
    3
  • fYear
    2002
  • fDate
    8/1/2002 12:00:00 AM
  • Firstpage
    790
  • Lastpage
    797
  • Abstract
    This paper proposes a parallel micro genetic algorithm (PMGA) for solving ramp rate constrained economic dispatch (ED) problems for generating units with nonmonotonically and monotonically increasing incremental cost (IC) functions. The developed PMGA algorithm is implemented on the thirty-two-processor Beowulf cluster with ethernet switches network on the systems with the number of generating units ranging from 10 to 80 over the entire dispatch periods. The PMGA algorithm carefully schedules its processors, computational loads, and synchronization overhead for the best performance. The speedup upper bounds and the synchronization overheads on the Beowulf cluster are shown on different system sizes and different migration frequencies. The proposed PMGA is shown to be viable to the online implementation of the constrained ED due to substantial generator fuel cost savings and high speedup upper bounds.
  • Keywords
    genetic algorithms; parallel algorithms; parallel processing; power engineering computing; power generation dispatch; power generation economics; synchronisation; constrained economic dispatch; ethernet switches network; generating units; generator fuel cost savings; high speedup upper bounds; monotonically increasing incremental cost functions; nonmonotonically increasing incremental cost functions; parallel micro genetic algorithm; ramp rate constrained economic dispatch; speedup upper bounds; synchronization overhead; synchronization overheads; thirty-two-processor Beowulf cluster; Clustering algorithms; Cost function; Ethernet networks; Frequency synchronization; Fuel economy; Genetic algorithms; Processor scheduling; Scheduling algorithm; Switches; Upper bound;
  • fLanguage
    English
  • Journal_Title
    Power Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0885-8950
  • Type

    jour

  • DOI
    10.1109/TPWRS.2002.800948
  • Filename
    1033727