Abstract :
The need for further sophistication of an already complex serial CAMAC control system at Fermilab lead to the development of an Auxiliary/Master CAMAC Crate Controller. The controller contains a Motorola 6800 microprocess- or, 2K bytes of RAM and 8K bytes of PROM memory. Bussed dataway lines are time shared with CAMAC signals to provide memory expansion and direct addressing of peripheral devices without the need of external cabling. The Auxiliary/Master Crate Controller (A/MCC) can function as either a Master, i.e., stand alone, crate controller or as an Auxiliary controller to Fermilab´s Serial Crate Controller (SCC). Two modules, one single and one double-width, make up an A/MCC. The double-width module contains the necessary crate controller hardware, i.e., read/write registers, station number registers, dataway cycle timing generator, etc. in addition to hardware providing input and output block transfer capabilities through the SCC. When the A/MCC is used as an auxiliary controller, the single-width module contains the microprocessor, RAM, PROM, MPU clock, and the timing and logic circuitry required for interleaving A/MCC and SCC dataway cycles as well as extending memory via dataway lines. When the A/MCC is functioning as a master crate controller, the first single-width module or one with DMA cycle-stealing transfer capabilities may be used. The module, in this latter case, need not and thus does not have dataway cycle interleaving capabilities. The microprocessor has one nonmaskable and one maskable vectored interrupt. The maskable interrupt has eight sublevels of vectored interrupts for ease of interrupt prioritizing and servicing.
