• DocumentCode
    822408
  • Title

    Device model approximation using 2N trees

  • Author

    Lewis, David M.

  • Author_Institution
    Dept. of Electr. Eng., Toronto Univ., Ont., Canada
  • Volume
    9
  • Issue
    1
  • fYear
    1990
  • fDate
    1/1/1990 12:00:00 AM
  • Firstpage
    30
  • Lastpage
    38
  • Abstract
    The application of 2N trees to device model approximation is described. The domain of the device model function is partitioned using a 2N tree, with smaller partitions where the function is more nonlinear. The function value associated with each corner of each partition is precomputed, and the function is evaluated by a given point by interpolation over the smallest partition that includes that point. This technique has the advantage that highly nonlinear functions can be modeled with modest space and time requirements. Exponential functions, such as the subthreshold behavior of FETs, can be accurately modeled. Accuracy levels of 1% are possible down to currents of 10-11 A. Table generation time is small; it is only a few minutes for a MOSFET model including subthreshold effects. This algorithm is especially suited for application to a hardware-accelerated device model evaluator. The design of a prototype that is capable of performing a device model evaluation of a SPICE level-2 model including subthreshold effects in 1 μs is described. Less detailed models, such as timing simulator models, can be evaluated in as little as 0.2 μs
  • Keywords
    circuit CAD; field effect transistors; insulated gate field effect transistors; semiconductor device models; trees (mathematics); 2N trees; FETs; MOSFET model; SPICE level-2 model; device model approximation; function value; hardware-accelerated device model evaluator; interpolation; nonlinear functions; subthreshold effects; timing simulator models; Circuit simulation; FETs; Hardware; Interpolation; MOSFET circuits; Performance evaluation; Prototypes; SPICE; Table lookup; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.45854
  • Filename
    45854