Title :
Fast effective heuristics for the graph bisectioning problem
Author :
Saab, Youssef G. ; Rao, Vasant B.
Author_Institution :
Coordinated Sci. Lab., Illinoi Univ., Urbana, IL, USA
fDate :
1/1/1990 12:00:00 AM
Abstract :
The graph bisectioning problem has several applications in VLSI layout, such as floorplanning and module placement. A sufficient condition for optimality of a given bisection is presented. This condition leads to an algorithm that always finds an optimal bisection for a certain class of graphs. A greedy approach is then used to develop a more powerful heuristic. On small random graphs with up to 20 vertices, one of the greedy algorithms generated the optimal bisection in each case considered. For very large graphs with 300 vertices or more, the algorithm generated bisections with costs within 30% of a lower bound previously derived. An adaptive algorithm that iteratively improves upon a given initial bisection of a graph is presented. Its performance is compared with that of the well-known Kernighan-Lin method on many random graphs with large numbers of vertices. The results indicate that the new adaptive heuristic produces bisections with costs within 2% of those produced by the Kernighan-Lin method (the costs were actually lower in about 70% of the cases) with a three times faster computation speed in most cases
Keywords :
VLSI; circuit layout; graph theory; Kernighan-Lin method; VLSI layout; adaptive algorithm; adaptive heuristic; computation speed; floorplanning; graph bisectioning problem; module placement; optimal bisection; random graphs; Adaptive algorithm; Costs; Design automation; Greedy algorithms; Iterative algorithms; Sufficient conditions; Symmetric matrices;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on