Title :
Efficient sequential test generation based on logic simulation
Author :
Sheng, Shuo ; Hsiao, Michael S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
Abstract :
In this article, we present an efficient logic-simulation-based test generator that executes significantly more quickly than its fault-simulation-based counterparts. This test generator´s fault coverage compares favorably with that of the latest techniques for large sequential circuits. It uses a genetic algorithm to achieve both high fault coverage and short test generation times
Keywords :
logic simulation; logic testing; sequential circuits; logic simulation; sequential circuits; sequential test generation; test generators; Circuit faults; Circuit noise; Circuit testing; Computational modeling; Flip-flops; Genetic algorithms; Logic testing; Noise generators; Noise measurement; Sequential analysis;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2002.1033793
