Title :
Area-efficient FPGA-based FFT processor
Author :
Sansaloni, T. ; Pérez-Pascual, A. ; Valls, J.
Author_Institution :
Dept. of Electron. Eng., Polytech. Univ. of Valencia, Grao De Gandia, Spain
Abstract :
A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ´twiddle factors´ sequentially leads to an area saving up to 35% with respect to other cores.
Keywords :
VLSI; digital arithmetic; digital signal processing chips; fast Fourier transforms; field programmable gate arrays; CORDIC operator; FPGA-based FFT processor; area-efficient FFT processor; butterfly architecture; decimation-in-frequency algorithm; fast Fourier transform; multiplication; programmable devices; radix-4 DIF algorithm;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20030892
