Title :
High performance dynamic logic incorporating gate voltage controlled keeper structure for wide fan-in gates
Author :
Jung, Seong-Ook ; Kang, Sung-Mo
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
fDate :
8/1/2002 12:00:00 AM
Abstract :
A new keeper structure for wide fan-in gates is proposed to optimise performance, noise- and skew-tolerance by controlling the gate voltage of the keeper transistor. Simulation results show that the proposed gate voltage controlled keeper scheme improves performance by 13.8 and 26.6% compared with the conventional keeper scheme for 16 and 32 bit wide fan-in dynamic gates
Keywords :
MOS logic circuits; circuit optimisation; integrated circuit design; leakage currents; logic gates; 16 bit; 32 bit; NMOS; dynamic logic; gate voltage; gate voltage controlled keeper structure; keeper transistor; leakage current; skew-tolerance; wide fan-in gates;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20020623
