DocumentCode
822960
Title
CMOS digital duty cycle correction circuit for multi-phase clock
Author
Jang, Y.C. ; Bae, S.J. ; Park, H.J.
Author_Institution
Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea
Volume
39
Issue
19
fYear
2003
Firstpage
1383
Lastpage
1384
Abstract
A digital duty cycle correction circuit with a fixed-delay rising-edge output is proposed for use in applications with the multi-phase clock and the standby mode. Two integrators are used in the duty cycle detector to eliminate the effect of reference voltage variations. The output duty cycle is adjusted to 50±0.25% throughout the input duty cycle range from 20% to 80% at the frequency of 1.25 GHz. 0.18 μm CMOS technology is used in this work.
Keywords
CMOS digital integrated circuits; high-speed integrated circuits; integrating circuits; timing circuits; 0.18 micron; 1.25 GHz; 1.8 V; 3.2 mW; 800 MHz to 1.7 GHz; CMOS technology; digital duty cycle correction circuit; duty cycle detector; fixed-delay rising-edge output; integrators; multi-phase clock; standby mode;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20030908
Filename
1244156
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