• DocumentCode
    822990
  • Title

    Reduced clock swing domino logic

  • Author

    Casu, M.R.

  • Author_Institution
    Dept. of Electron., Politecnico di Torino, Italy
  • Volume
    38
  • Issue
    16
  • fYear
    2002
  • fDate
    8/1/2002 12:00:00 AM
  • Firstpage
    860
  • Lastpage
    861
  • Abstract
    A reduced clock swing domino logic gate for 50% reduction in power consumption in clock networks is presented. The original full swing gate works properly at reduced swing with a better noise tolerance and small loss of performance while simple resizing allows the same speed, power and noise figures
  • Keywords
    clocks; integrated circuit noise; logic gates; clock swing; domino logic gate; noise figure; noise tolerance; power consumption; resizing method;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20020632
  • Filename
    1033810
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=822990