Transistor-level estimation of worst-case delays in MOS VLSI circuits

The authors present three algorithms for efficient worst-case delay estimation in transistor groups using transistor-level delay models and timing simulation techniques. The first algorithm, dynamic path selection (DPS), determines the path with the longest delay in a transistor group. If the group consists of series-parallel transistor combinations, the time complexity is linear. The second algorithm, delay subnetwork enumeration (DSE), complements the DPS method by taking into account logic dependencies. The paths with the shortest delay are computed using the dynamic cut selection (DCS) algorithm. These techniques have been implemented in the static timing analyzer TAMIA to provide fast and accurate worst-case delay estimation for digital CMOS circuits