Parallel Prefix Modulo- Adder via Double Representation of Residues in [0,

The most popular modulus in residue number systems (RNS), next to power-of-two modulus, are those of the form (2ⁿ-1). However, in RNS applications that require a larger dynamic range, without increasing the n parameter, modulus of the form (2ⁿ-3) are gaining popularity. Nevertheless, latency-balanced computational channels in RNS arithmetic systems are desirable. Ripple-carry modulo-(2ⁿ-1) adders are realized simply as one´s complement adders, where (2ⁿ-1) serves as a second representation for 0. However, the same single n-bit adder realization is not possible for modulo (2ⁿ-3). Given that the efficient parallel prefix realization of modulo-(2ⁿ-1) adders exists, whose latency is compatible with similar modulo-2ⁿ adders, we are motivated to design latency-compatible parallel prefix modulo-(2ⁿ-3) adders. In this brief, we propose the fastest of such adders, where residues in {0, 1, 2} can be represented also as excess-(2ⁿ-3) encoding (i.e., {2ⁿ-3, 2ⁿ-2, 2ⁿ-1}, respectively) . The delay and area overhead of the proposed adder with respect to the base modulo-(2ⁿ-1) adder is only one extra gate in the critical delay path and, at most, 20% more area. In very rare cases that both operands are excess-(2ⁿ-3), augmenting the proposed adder with few extra gates leads to correct sum. The analytical results are confirmed by synthesis via Synopsys Design Compiler.