Title :
Asynchronous VLSI architecture for adaptive echo cancellation
Author :
Mackey, R.P. ; Rodriguez, J.J. ; Carothers, J.D. ; Vrudhula, S.B.K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
fDate :
4/11/1996 12:00:00 AM
Abstract :
A single chip, 128 coefficient, asynchronous echo canceller is presented. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate >206.5 kHz
Keywords :
FIR filters; VLSI; adaptive filters; asynchronous circuits; echo suppression; least mean squares methods; pipeline processing; FIR filter; adaptive echo cancellation; asynchronous VLSI architecture; filtered output; pipelined circuit; power-of-two modified LMS algorithm; sampling rate;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960509
