FPGA Implementation of an Iterative Receiver for MIMO-OFDM Systems

Author

Boher, Laurent ; Rabineau, Rodrigue ; Hélard, Maryline

Author_Institution

RESA/WIN Dept., Orange Labs., Cesson-Sevigne

Volume

26

Issue

6

fYear

2008

fDate

8/1/2008 12:00:00 AM

Firstpage

857

Lastpage

866

Abstract

Today iterative receivers have proved their efficiency in cancelling interference within the field of wireless communications. However their complexity is often seen as a brake for their use in real systems. In this paper an efficient iterative receiver real-time implementation for a 4 times 4 MIMO system is presented. An architecture of MMSE iterative receiver for MIMO-OFDM systems is proposed to limit latency and complexity due to iterative process: MMSE equalization implementation is realized using CORDIC operators; the scheduling between MIMO detection and channel decoding is optimized and specific interleaving functions are introduced to reduce latency and accelerate the convergence process. The implemented receiver is integrated in a real-time FPGA testbench and compared in terms of complexity and performance with a non iterative solution.

Keywords

MIMO communication; OFDM modulation; convergence of numerical methods; field programmable gate arrays; iterative methods; least mean squares methods; radio receivers; radiofrequency interference; signal detection; wireless channels; CORDIC operator; FPGA implementation; MIMO detection; MIMO-OFDM systems; MMSE equalization; channel decoding; convergence process; interference cancellation; interleaving functions; iterative receiver; minimum mean square error method; multiple input multiple output systems; orthogonal frequency division multiplexing; wireless communication;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/JSAC.2008.080803

Filename

4586303